Hardware Assisted Verification
Four use-modes
- Transaction-based acceleration
- Simulation acceleration
- In-circuit emulation
- Synthesizable testbench
Industry best-in-class features and capabilities
- One to three users
- Up to 16M gates
- Up to 1.5MHz DUT clock
- Automatic 100% DUT visibility at highest performance with no recompile
- 2,048 user I/O pins
- 15 asynchronous clock domains
- Ultra-fast distributable compile
Two Chassis
- Solo
- Trio rack-mount
Veloce by Mentor Graphics
Leasing and Sales-Technical Consulting
Hardware Assisted Design Verification
Veloce Solo and Trio Sales
Hardware Assisted Verification / Methodology Consulting
Leasing of Customer Remote Access Time on Veloce Solo
VELOCE OVERVIEW AND DEMO PRESENTATIONS
Wade Stone
Owner, Sparres
Methodology
Advanced high-speed simulation-class verification
- Transaction-based performance optimization
- SoC early software development/debug
- SystemVerilog/SystemC
- OVM/TLM
- Algorithmic testbench re-use
VELOCE APPLICATIONS
Sparres Provides a Full Suite of Veloce HW Assisted Verification Consulting services
- Product Deployment and Design Verification Services
- Transaction-Based Methodology Insertion
- Customer Design/Testbench Bring-Up Assistance
- Veloce Product/Solutions Training
- Custom HAV Solutions Development
The Veloce SoC Emulation System
- TBX
- HDL-Link
- 0-IN Assertions
- JTAG
- ICE